In the NAND type flash memory device there is a problem whereby in order to meet the two demands of large capacity and high speed, a page length has increased and this has caused a great increase in electric current. In the present NAND type flash memory, the bit line shield type SA (SA; sense amp) method or the all bit read out type SA method are widely known.
In both of these methods, because more than 4 Kbytes of data length is written at once at the time of program operation the peak current in order to charge a bit line increases. In the bit line shield type SA method and the all bit line read out type SA method, especially since nearly 90% of a bit lines capacity is the capacity of the bit line that adjoins it, in the bit line data, because the required charge to charge a bit line where “1” data and “0” data are lined in an alternating pattern increases, the peak current increases.
Also, in the NAND type flash memory device which uses the all bit line read out type SA, the consumption of current at the time of read also increases. Because this is to suppress bit line noise in the all bit line read out type SA method, in order to discharge cell current so that the bit line voltage becomes constant it is unavoidable that current consumption will increase, particularly, as the number of erasure state cells increase so does current consumption.
In both the bit line shield type SA method and the all bit line read out type SA method, as the length of a simultaneous write page becomes greater at the time of program operation so does the peak current for the bit line charge. The peak current is designed so that at a simultaneous write of 4 Kbyte page length, about 100 mA is suppressed. If the page length increases by 2 or 4 times and if the bit line charge speed is to be maintained then the peak current will increase to over 100 mA. Attempting to suppress the peak current will make the bit line charge speed slower.
According to the write method by hot-carrier injection used in a NOR flash memory for example, the number of simultaneous writes is restricted by the write current to the cell itself. However, in the NAND type flash memory device, because the write method to the cell is conducted by a tunneling effect the write current to the cell itself does not become a problem but the current for the bit line charge does. Also, a semiconductor memory device which reduces data read out time and standby power consumption (for example, Japanese Patent application Laid Open No. 2005-44456) is proposed.